Abstract:-
 

In
the latest designs of VLSI, power dissipation is a main advantage to reduce it.
As technology is growing day by day our chip size is to be reduce, less time
delay and less power consumption of any system  has become priority. In VLSI, sequential
Circuit takes a major  part to optimize
the power and to reduce the chip size. A counter is a sequential circuit having
major applications in microcontroller such that digital to analog converters
signal generators, digital alarm clock to computer memory  pointers. In this paper  low power, 4-bit Johnson Counter is to be
designed by using clock gating Techniques. In this paper, we analyzed that the
performance of proposed Johnson counter is better than that of conventional
Johnson counter.

Keyword–Johnson
counter, clock gating, power          
dissipation, sequential
circuit.

1.
INTRODUCTION

Counters
are very important part of digital system. It is widely used component in
digital system. Counters are used to count the number of clock pulses
synchronously. Counter is a set of flip-flops that change their states in a
specific manner to generate a particular sequences. These sequences could be
associated with the number of times events can occurs. Counters are based on
time that have constant and fast nature are required in designs of VLSI with
high speed and to optimize the power. Counters are of synchronous type and
Asynchronous type. Synchronous
types of counter are important for providing different data series in a
synchronous manner to a system.

 

 

 

 

Johnson Counter is an important
part in Digital to Analog converter, Johnson counter is one such counter system
which provides data sequenceinitsdistinctmanner.                                                  
    In this
paper, we design a low power dissipation of Johnson counter using a clock
gating Technique is described here. As we know that continuous switching of
clock is the major supplier of power dissipation. Johnson counter is basically
a Ring counter with complement output of last shift register is feedback to
input of first shift register. Johnson counter is also known as switched tail
ring counter, twisted ring counter, walking ring counter. The basic difference
between ring  counter and Johnson counter
is that Johnson counter is self started counter with initial value contained
‘0000’.

2.
CLOCK GATING

Clock
gating is used to reduce dynamic power dissipation. It is used to block the
unwanted clock pulse transitions where the output bit remains constant i.e
output bits are not toggling the clock It Works by taking the enable conditions
attached to registers, and uses them  to
gate the clocks. There are two types
of clock gating styles available. They are:

1)
Latch-based clock gating          

2)
Latch-free clock gating.

 

 

1) Latch-based
clock gating  

In
latch based clock gating, it Uses a simple AND or OR gate. Glitches are
inevitable i.e. Glitch is any unwanted clock pulse that may occur during the
triggering of clock pulse. The
figure below shows a flip-flop receiving a enable signal and a clock signal; if
there is some glitch (unwanted change of state) in clock, it will take it as a
real clock edge and latch the data to its output. However, if the pulse is too
small, the data may not propagate properly to output and the flop may go met
stable. It is less used.

Fig:1 Latch based
clock gating

2) Latch-free clock
gating.

It
adds a level-sensitive latch. It holds the enable signal from the active edge
of the clock until the En D Q inactive edge of the clock D Q It produced less
glitch CK Gated CK clock. It Easy adoption by EDA  tools.

Fig:2 Latch free
clock gating

.

 

3. CONVENTIONAL JOHNSON
COUNTER

In
this section, the design and output of conventional Johnson counter is
described. Johnson counter is nothing but a ring counter with its last output
being inverted and fed to the input at first Flip-flop. D or J-K flip flop in
master slave configuration are used in the Johnson counter to shift the data
synchronously as per the output sequence of the counter. The output counting
pattern of Johnson counter is shown in the table described below (Table.1).

Clock    pulse

Q3

Q2

Q1

Q0

1

0

0

0

0

2

0

0

0

1

3

0

0

1

1

4

0

1

1

1

5

1

1

1

1

6

1

1

1

1

7

1

1

0

0

8

1

0

0

0

 

 

 

 

 

Table:1
Output pattern of 4-bit Johnson counter.

4.
POWER CLOCK GATED DESIGN

In
this section, clock gated Johnson counter is explained which eliminated the number
of inputs

.
Hence, power is reduced. A clock gating logic comprises between logic gates.

5.
SIMULATION RESULT

The
Clock Gated Johnson counter has been designed. The output waveform is shown
below. The circuits are simulated using Xilinx 14.1 simulation tool.
Simulations are done on the time delay 0.01ns. 

 

6.
CONCLUSION

 The proposed design shows reduction in the
power  of the design which has clock
gating logic in it. Due to the use of clock gating we have achieved a power
reduction.

REFERENCES

1Sani
Md. Ismail,Mohd. M.Rehman,”A design scheme of johnson counter with efficient
clock gating”,IEEE transaction on circuits and system,2012.

2
Sani Md. Ismail, A B M Saadmaan Rahman, Farha Tamanna Islam “Low Power
Design of Johnson Counter Using Clock Gating” from
978-1-4673-48362/12/$31.00 ©2012 IEEE.

3
M. Pedram, “Power minimization in IC design: Principles and applications”, ACM
Trans. Design Automation, vol. 1, no. 1, pp. 3-56, Jan. 1996.

4
M. Pedram, Q. Wu and X. Wu, “A new design of double edge triggered flip-flops”,
In Proc. Of ASP-DAC, Yokohama, 417-421, February, 1998.

 5 X. Wu and Massoud Pedram, “Low power
sequential circuit design using priority encoding and clock gating”, Power
Electronics and Design, 2000. ISLPED ’00. Proceedings of the 2000 International
Symposium on, 143-148, July 2000.

 

 

 

 

 

 

 

 

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