of Architecture and Programming Model of 8086
Microprocessor is an enhanced version of 8085 Microprocessor. It is a 16-bit
microprocessor which has 16 data lines and 20 address lines. 8086
microprocessor can handle 2^20 memory locations, which is equivalent to 1MB. It
supports two operating modes:
Maximum operating mode: This mode is suitable for system having more than one
Minimum operating mode: This mode is suitable for system having only one
Features of 8086 microprocessor:
features of 8086 microprocessor are as follows:
It has an instruction queue, which can store 6 instruction bytes from the
It uses two stages of pipelining: Fetch and Execute.
In fetch stage, 6 bytes of instructions is fetched and stored in the queue.
These instructions are then executed in the execute stage.
It has 16-bit ALU, 16-bit internal registers, internal data bus and 16-bit
external data bus
Architecture of 8086 microprocessor:
8086 microprocessor functional units:
microprocessor is divided into two functional units:
Execution Unit (EU)
Bus Interface Unit (BIU)
Execution Unit (EU):
execution gives instructions to BIU telling from where to fetch the data,
decode and execute those instructions. Its function is to perform operations on
the data provided with the help of instruction decoder and ALU (Arithmetic and
Logic Unit). It performs operations on the data through BIU. The parts of EU
are as follows:
handles all the arithmetic and logical operations.
is a 16-bit register that changes its status according to the result stored in
the accumulator. It consists of 9 flags and are divided into two groups:
represents the result of the last arithmetic or logical instruction executed.
There are 6 conditional flags:
flag: This fag is used when a carry is generated from the MSB (Most Significant
Bit).This indicates an overflow condition for arithmetic operations. CF=1 when
a carry is generated and CF=0 when carry is not generated.
flag: The processor uses this flag to perform binary to BCD conversion. The
flag is set when a carry/borrow from lower nibble to upper nibble is generated
due to an operation performed at ALU.
flag: This flag is used to indicate the parity of the result. If there are even
number of 1s, the flag is set and if odd number of 1s are present, the flag is
flag: ZF=1 when the result of any arithmetic or logical operation is zero, else
flag: This flag holds the sign of the result. SF=1 when the result is negative,
flag: This flag represents the result when the system capacity is exceeded.
flag controls the operations of the execution unit. There are 3 control flags:
flag: It is used for stepwise execution of the program and allows the execution
of only one instruction at a time for debugging. If TF=1, then the program can
be run in single step.
flag: It is used to allow or prevent the interruption of a program. For
interrupt enabled condition, IF=1, else IF=0.
flag: It is used in string operation. It is set when string bytes are accessed
from higher memory address to lower memory address and vice versa.
General Purpose Register:
are 8 general purpose registers. They are used in pairs to store 16-bit data.
These registers are referred to the AX, BX, CX and DX.
register: Known as accumulator register. It is used to store the operands for
register: It is used as base register. It is used to store the starting base
address of the memory area.
3. CX register: It is known as the
counter. It is used to store the loop counter.
4. DX register: This register holds the I/O port
address for I/O instruction.
Stack pointer register:
holds the address from the start of the segment to the memory location.
Bus Interface Unit (BIU):
takes care of all data and addresses transfers on the buses for the EU. EU has
no direct connection with the System Buses, so this is possible with the BIU.
EU and BIU are connected with the Internal Bus. The parts of BIU are as
queue: BIU contains the instruction queue. It gets upto 6 bytes of instructions
and stores them in the instruction queue. After executing the instructions, EU
reads the next instruction from the instruction queue. Fetching the next
instruction during the execution of current instruction is called pipelining.
Register: There are 4 segment buses: CS, DS, SS and ES. It also has one pointer
register IP, which holds the address of the next instruction which is to be
executed by the EU.
CS (Code Segment): It is used for
addressing a memory location in the code segment of the code segment of the
DS (Data Segment): It consists of data
used by the program and is accessed in the data by segment by an offset
SS (Stack Segment): It handles memory to
store data and addresses during execution.
ES (Extra Segment): It is used to hold the
data which cannot be accommodated in the Data Segment.
Pointer: It is used to hold the address of the next instruction to be executed.